TY - GEN
T1 - Synchronous bus arbitration with constant logic per module
AU - Alnuweiri, Hussein M.
PY - 1994
Y1 - 1994
N2 - A novel technique for distributed synchronous bus arbitration is presented in this paper. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps)., only the width of the arbitration bus must be increased in this case.
AB - A novel technique for distributed synchronous bus arbitration is presented in this paper. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps)., only the width of the arbitration bus must be increased in this case.
UR - http://www.scopus.com/inward/record.url?scp=0028058326&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0028058326
SN - 0818656026
T3 - Proceedings of the International Conference on Parallel Processing
SP - 35
EP - 41
BT - Proceedings of the International Conference on Parallel Processing
PB - Publ by IEEE
T2 - Proceedings of the 8th International Parallel Processing Symposium
Y2 - 26 April 1994 through 29 April 1994
ER -