TY - GEN
T1 - VLSI implementation of a binary neural network-two case studies
AU - Bermak, A.
AU - Austin, J.
N1 - Publisher Copyright:
© 1999 IEEE.
PY - 1999
Y1 - 1999
N2 - A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n×m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters. Since we are interested in the VLSI implementation of such networks, hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.
AB - A comparison between a bit-level and a conventional VLSI implementation of a binary neural network is presented. This network is based on Correlation Matrix Memory (CMM) that stores relationships between pairs of binary vectors. The bit-level architecture consists of an n×m array of bit-level processors holding the storage and computation elements. The conventional CMM architecture consists of a RAM memory holding the CMM storage and an array of counters. Since we are interested in the VLSI implementation of such networks, hardware complexities and speeds of both bit-level and conventional architecture were compared by using VLSI tools. It is shown that a significant speedup is achieved by using the bit-level architecture since the speed of this last configuration is not limited by the memory addressing delay. Moreover, the bit-level architecture is very simple and reduces the bus/routing, making the architecture suitable for VLSI implementation. The main drawback of such an approach compared to the conventional one is the demand for a high number of adders for dealing with a large number of inputs.
KW - Binary neural networks
KW - Bit-level architecture
KW - Internal storage processors
KW - VLSI implementation
UR - http://www.scopus.com/inward/record.url?scp=78049232371&partnerID=8YFLogxK
U2 - 10.1109/MN.1999.758889
DO - 10.1109/MN.1999.758889
M3 - Conference contribution
AN - SCOPUS:78049232371
T3 - Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999
SP - 374
EP - 379
BT - Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999
Y2 - 7 April 1999 through 9 April 1999
ER -