VLSI implementation of pipelined sphere decoding with early termination

The sphere decoding algorithm allows to implement the detection stage in multiple-input multiple-output communication systems with maximum likelihood error rate performance, while the average computational complexity of the algorithms remains far below an exhaustive search. This paper addresses two important problems associated with the practical implementation of sphere decoding: the mitigation of the error rate performance caused by constraining the maximum instantaneous decoding effort and the introduction of pipelining into recursive one-node-per-cycle VLSI architectures for depth-first sphere decoding. The result of this work is a sphere decoder implementation for a 4×4 system with 16-QAM modulation in a 0.13 μm technology that achieves a guaranteed minimum throughput of 761 Mbps.